Several power devices are designed with deep trench formations in order to reduce chip size. Usually, the trench will be covered with a dielectric layer (e.g., oxide or nitride) for electrical isolation. Afterwards, the dielectric layer has to be removed at the bottom of the trench to enable electrical contact from the backside of the wafer. Mostly, from device point of view it is mandatory to leave the dielectric layer at the top of the trench. Unfortunately, the etch rate at top is always higher than on bottom due to ARDE (ARDE=aspect ratio depended etching).